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BU9832GUL-W (8Kbit)
● Command mode
Datasheet
Command
Contents
Ope code
WREN
WRDI
READ
WRITE
RDSR
WRSR
Write enable
Write disable
Read
Write
Read status register
Write status register
Write enable command
Write disable command
Read command
Write command
Status register read command
Status register write command
0000
0000
0000
0000
0000
0000
0110
0100
0011
0010
0101
0001
CS
● Timing chart
1. Write enable (WREN) / disable (WRDI) cycle
? WREN (WRITE ENABLE): Write enable
―――
CS
SCK
SI
0
0
0
1
0
2
0
3
0
4
1
5
1
6
0
7
CS ―
High-Z
SO
Figure 33. Write enable command
? WRDI (WRITE DISABLE): Write disable
――
CS
SCK
SI
0
0
0
1
0
2
0
3
0
4
1
5
0
6
0
7
High-Z
SO
Figure 34. Write disable
○ This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it
is set to write disable status by write disable command. As for these commands, set CS LOW, and then input the
respective ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks,
command becomes valid.
When to carry out write and write status register command, it is necessary to set write enable status by the write
enable command. If write or write status register command is input in the write disable status, commands are cancelled.
And even in the write enable status, once write and write status register command is executed once, it gets in the write
disable status. After power on, this IC is in write disable status.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
15/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001
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